DRAM devices are subjected to numerous tests at various stages of manufacture. Tests are conducted on a wafer of DRAM integrated circuits (ICs) during production, and at the chip level after wafer slicing. Certain common DRAM tests are called wordline (WL) toggle tests and critical row precharge time (TRP) tests.
WL toggle tests are time consuming in nature and typically run on Test During Burn In (TBDI) systems that operate at clock speeds of a few MHz, whereas the DRAM device clock speeds are continually increasing and already at the hundreds of MHz. Thus, current methods for burn-in WL toggle testing are limited by the slow clock rate of the TBDI systems since toggling of WLs is simply a sequence of activate (ACT) and precharge (PRE) commands as shown in FIG. 1. For example, the clock rate of a typical TBDI system is approximately 5 MHz and for a wafer test system is approximately 60 MHz. Currently, DRAMs have clock rates of 333 MHz clock and greater. FIG. 1 shows that the row address is incremented by one, but it should be understood that any row address increment sequence is possible. The rate of testing with existing testing techniques cannot approach the normal operation rate of the DRAM device. Similarly, in wafer test devices are limited in their testing speed because they are driven by a clock that is much slower than the clock rate of the chips on the wafer.
It is desirable to provide a test mode or programmable feature of a DRAM device that facilitates much faster testing during ACT-PRE cycles of the DRAM device, and is not limited by the clock rate of the test equipment.